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1 fn6423.2 caution: these devices are sensitive to electrostatic discharge ; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) and xdcp are registered trademarks of int ersil americas llc copyright intersil americas llc 2007, 2008, 2015. all rights re served all other trademarks mentioned are the property of their respec tive owners. isl22343 quad digitally controlled potentiometer (xdcp?) low noise, low power, i 2 c bus, 256 taps the isl22343 integrates f our digitally controlled potentiometers (dcp), control logic and non-volatile memory on a monolithic cmos i ntegrated circuit. the digitally controlled potent iometer is implemented with a combination of resistor el ements and cmos switches. the position of the wipers are controlled by the user through the i 2 c bus interface. the potentiometer has an associated volatile wiper register (wri) and a non-volatile initial value register (ivri) that can be directly written to and read by the user. the contents of the w ri control the position of the corresponding wiper. at power up the device recalls the contents of the dcps ivri to the correspondent wri. the isl22343 also has 11 ge neral purpose non-volatile registers that can b e used as storage of lookup table for multiple wiper position or any other valuable information. the isl22343 features a dual supply, that is beneficial for applications requiring a bipolar range for dcp terminals between v- and vcc. each dcp can be used as three- terminal potentiometers or as two-terminal vari able resistors in a wide variety of applications including control, parameter adjustments, and signal processing. features ? four potentiomete rs in one package ? 256 resistor taps ?i 2 c serial interface - three address pins, up to eight devices per bus ? non-volatile eeprom sto rage of wiper position ? 11 general purpose no n-volatile registers ? high reliability - endurance: 1,000,000 data c hanges per bit per register - register data retention: 50 years @ t ??? 55 c ? wiper resistance: 70 ? typical @ 1ma ? standby current <4a max ? shutdown current <4a max ? dual power supply - vcc = 2.25v to 5.5v - v- = -2.25v to -5.5v ?10k ?? 50k ?? or 100k ? total resistance ? extended industrial temperature range: -40c to +125 c ? 20 ld tssop or 20 ld qfn ? pb-free (rohs compliant) ordering information part number (notes 1, 2) part marking resistance option (k ? ) temp. range (c) package (pb-free) pkg. dwg. # isl22343tfv20z (no longer available, recommended replacement: isl22343wfr20z-tk ) 22343 tfvz 100 -40 to +125 20 ld tssop m20.173 isl22343tfr20z (no longer available, recommended replacement: isl22343wfr20z-tk 22343 tfrz 100 -40 to +125 20 ld qfn l20.5x5 isl22343ufv20z (no longer available, recommended replacement: isl22343wfr20z-tk 22343 ufvz 50 -40 to +125 20 ld tssop m20.173 isl22343ufr20z (no longer available, recommended replacement: isl22343wfr20z-tk 22343 ufrz 50 -40 to +125 20 ld qfn l20.5x5 ISL22343WFV20Z 22343 wfvz 10 -40 to +125 20 ld tssop m20.173 isl22343wfr20z 22343 wfrz 10 -40 to +125 20 ld qfn l20.5x5 notes: 1. these intersil pb-free plasti c packaged products employ speci al pb-free material sets; molding compounds/die attach material s and 100% matte tin plate plus anneal - e3 termi nation finish, which is rohs co mpliant and compatible with both snpb and pb-free soldering ope rations. intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. add -tk suffix for tape and reel. please refer to tb347 for details on reel specifications data sheet august 17, 2015
2 fn6423.2 august 17, 2015 block diagram i 2 c interface vcc rh0 rh1 rh2 rh3 gnd rl0 rl1 rl2 rl3 rw0 rw1 rw2 rw3 scl sda a0 a1 power-up, control and status logic non-volatile registers wr3 wr2 wr1 wr0 v- a2 isl22343 (20 lead tssop) top view isl22343 (20 lead qfn) top view 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 rh3 rl3 rw3 a2 scl sda rw2 gnd rl2 rh2 rw0 rh0 v- vcc rl0 a1 a0 rh1 rl1 rw1 rw2 sda a0 a1 rl2 rh2 rh3 rl3 rw0 rw1 v- a2 vcc rl0 rw3 scl rh0 gnd rh1 rl1 1 2 3 4 5 678910 15 14 13 12 11 20 19 18 17 16 isl22343
3 fn6423.2 august 17, 2015 pin descriptions tssop pin qfn pin symbol description 1 19 rh3 high terminal of dcp3 2 20 rl3 low terminal of dcp3 3 1 rw3 wiper terminal of dcp3 4 2 a2 device address input for the i 2 c interface 5 3 scl open drain i 2 c interface clock input 6 4 sda open drain serial data i/o for the i 2 c interface 7 5 gnd device ground pin 8 6 rw2 wiper terminal of dcp2 9 7 rl2 low terminal of dcp2 10 8 rh2 high terminal of dcp2 11 9 rw1 wiper terminal of dcp1 12 10 rl1 low terminal of dcp1 13 11 rh1 high terminal of dcp1 14 12 a0 device address input for the i 2 c interface 15 13 a1 device address input for the i 2 c interface 16 14 vcc positive power supply pin 17 15 v- negative power supply pin 18 16 rh0 high terminal of dcp0 19 17 rl0 low terminal of dcp0 20 18 rw0 wiper terminal of dcp0 epad* exposed die pad internally connected to v- note: *pcb thermal land for qfn epad should be connected to v- p lane or left floating. for more information refer to http://www.intersil.com/data/tb/tb389.pdf isl22343
4 fn6423.2 august 17, 2015 absolute maximum ratings thermal information storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage at any digital interface pin with respect to gnd . . . . . . . . . . . . . . . . . . . . . -0 .3v to v cc +0.3 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6v to 0.3v voltage at any dcp pin with respect to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v- to v cc i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma latchup . . . . . . . . . . . . . . . . . . . . . . . . . class ii, level a at +125c esd human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400v thermal resistance (typical, note 3) ? ja (c/w) ? jc (c/w) 20 lead tssop . . . . . . . . . . . . . . . . . . . . . . . .95 n/ a 20 lead qfn (note 4) . . . . . . . . . . . . . . . . . . .32 3.0 maximum junction temperatur e (plastic package) . . . . . . . +1 50c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature range (full industrial) . . . . . . . . . . . .-40 c to +125c power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mw v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25v to 5.5v v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.25v to -5.5v max wiper current iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ma caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 3. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. 4. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. analog specifications over recommended operating conditions unless otherwise stated. symbol parameter test conditions min (note 21) typ (note 5) max (note 21) unit r total rhi to rli resistance w option 10 k ? u option 50 k ? t option 100 k ? rhi to rli resistance tolerance -20 +20 % end-to-end temperature coefficient w option 85 ppm/c u, t option 45 ppm/c v rhi , v rli dcp terminal voltage v rh and v rl to gnd v- v cc v r w wiper resistance rh - floating, v rl = v-, force iw current to the wiper, i w = (v cc - v rl )/r total 70 250 ? c h /c l /c w (note 19) potentiometer capacitance see macro model below. 10/10/25 pf i lkgdcp leakage on dcp pins voltage at pin from v- to v cc 0.1 1 a voltage divider mode (v- @ rli; v cc @ rhi; measured at rwi, unloaded) inl (note 10) integral non-linearity w option -1.5 0.5 1.5 lsb (note 6) u, t option -1.0 0.2 1.0 lsb (note 6) dnl (note 9) differential non-linearity monot onic over all tap positions, w option -1.0 0.4 1.0 lsb (note 6) u, t option -0.5 0.15 0.5 lsb (note 6) zserror (note 7) zero-scale error w option 0 1 5 lsb (note 6) u, t option 0 0.1 2 fserror (note 8) full-scale error w option -5 -2 0 lsb (note 6) u, t option -2 -0.2 0 isl22343
5 fn6423.2 august 17, 2015 v match (note 11) dcp-to-dcp matching wipers at the same tap position, the same voltage at all rh terminals and the same voltage at all rl terminals -2 2 lsb (note 6) tc v (note 12) ratiometric temperature coefficient dcp register set to 80 hex 4 ppm/c f cutoff (note 19) -3db cut off frequency wiper at m idpoint (80hex) w option (10k) 1 000 khz wiper at midpoint (80hex) u option (50k) 250 khz wiper at midpoint (80hex) t option (100k) 120 khz resistor mode (measurements between rwi and rli with rhi not connected, or be tween rwi and rhi with rli not connected) rinl (note 16) integral non-linearity w option -3 1 3 mi (note 13) u, t option -1 0.3 1 mi (note 13) rdnl (note 15) differential non-linearity w option -1.5 0.5 1.5 mi (note 13) u, t option -0.5 0.04 0.5 mi (note 13) roffset (note 14) offset w option 0 1 5 mi (note 13) u, t option 0 0.25 2 mi (note 13) r match (note 17) dcp-to-dcp matching wipers at the same tap position with the same terminal voltages -3 3 mi (note 13) tc r (notes 18, 19) resistance temperature coefficient dcp register set between 32 h ex and ffhex 40 ppm/c analog specifications over recommended operating conditions unless otherwise stated. (continued) symbol parameter test conditions min (note 21) typ (note 5) max (note 21) unit operating specifications over the recommended operating c onditions unless otherwise spec ified. symbol parameter test conditions min (note 21) typ (note 5) max (note 21) unit i cc1 v cc supply current (volatile write/read) v cc = 5.5v, f scl = 400khz; (for i 2 c active, read and volatile write states only) 0.006 0.5 ma v cc = 2.25v, f scl = 400khz; (for i 2 c active, read and volatile write states only) 0.003 0.25 ma i v-1 v- supply current (volatile write/read) v- = -5.5v, v cc = 5.5v, f scl = 400khz; (for i 2 c active, read and volatile write states only) -0.5 -0.012 ma v- = -2.25v, v cc = 2.25v, f scl = 400khz; (for i 2 c active, read and volatile write states only) -0.25 -0.045 ma i cc2 v cc supply current (non- volatile write/read) v cc = 5.5v, v- = 5.5v, f scl = 400khz; (for i 2 c active, read and non-volatile write states only) 1.0 2.0 ma v cc = 2.25v, v- = -2.25v, f scl = 400khz; (for i 2 c active, read and non-volatile write states only) 0.3 1.0 ma i v-2 v- supply current (non-volatile write/read) v- = -5.5v, v cc = 5.5v, f scl = 400khz; (for i 2 c active, read and non-volatile write states only) -2.0 -1.2 ma v- supply current (non-volatile write/read) v- = -2.25v, v cc = 2.25v, f scl = 400khz; (for i 2 c active, read and non-volatile write states only) -1.0 -0.4 ma isl22343
6 fn6423.2 august 17, 2015 i sb v cc current (standby) v cc = +5.5v, v- = -5.5v @ +85c, i 2 c interface in standby state 0.5 2.0 a v cc = +5.5v, v- = -5.5v @ +125c, i 2 c interface in standby state 1.0 4.0 a v cc = +2.25v, v- = -2.25v @ +85c, i 2 c interface in standby state 0.2 1.0 a v cc = +2.25v, v- = -2.25v @ +125c, i 2 c interface in standby state 0.5 2.0 a i v-sb v- current (standby) v- = -5.5v, v cc = +5.5v @ +85c, i 2 c interface in standby state -4.0 -0.7 a v- = -5.5v, v cc = +5.5v @ +125c, i 2 c interface in standby state -5.0 -1.5 a v- = -2.25v, v cc = +2.25v @ +85c, i 2 c interface in standby state -2.0 -0.3 a v- = -2.25v, v cc = +2.25v @ +125c, i 2 c interface in standby state -3.0 -0.4 a i sd v cc current (shutdown) v cc = +5.5v, v- = -5.5v @ +85c, i 2 c interface in standby state 0.5 2.0 a v cc = +5.5v, v- = -5.5v @ +125c, i 2 c interface in standby state 1.0 4.0 a v cc = +2.25v, v- = -2.25v @ +85c, i 2 c interface in standby state 0.2 1.0 a v cc = +2.25v, v- = -2.25v @ +125c, i 2 c interface in standby state 0.5 2.0 a i v-sd v- current (shutdown) v- = -5.5v, v cc = +5.5v @ +85c, i 2 c interface in standby state -4.0 -0.7 a v- = -5.5v, v cc = +5.5v @ +125c, i 2 c interface in standby state -5.0 -1.5 a v- = -2.25v, v cc = +2.25v @ +85c, i 2 c interface in standby state -2.0 -0.3 a v- = -2.25v, v cc = +2.25v @ +125c, i 2 c interface in standby state -3.0 -0.4 a i lkgdig leakage current, at pins a0, a1, a2, sda, and scl voltage at pin from gnd to v cc -1 1 a t wrt (note 19) dcp wiper response time scl falling edge of last bit of dcp data byte to wiper new position 1.5 s t shdnrec (note 19) dcp recall time from shutdown mode scl falling edge of last bit of acr data byte to wiper stored position and rh connection 1.5 s vpor power-on recall voltage minimum v cc at which memory recall occurs 1.9 2.1 v vccramp v cc ramp rate 0.2 v/ms t d power-up delay v cc above vpor, to dcp initial value register recall completed, and i 2 c interface in standby state 5ms eeprom specification eeprom endurance 1,000,000 cycles eeprom retention temperature t ?? +55 c50years t wc (note 20) non-volatile write cycle time 12 20 ms operating specifications over the recommended operating c onditions unless otherwise spec ified. (continued) symbol parameter test conditions min (note 21) typ (note 5) max (note 21) unit isl22343
7 fn6423.2 august 17, 2015 serial interface specs v il a1, a0, a2, sda, and scl input buffer low voltage 0.3*v cc v v ih a1, a0, a2, sda, and scl input buffer high voltage 0.7*v cc v hysteresis (note 19) sda and scl input buffer hysteresis 0.05*v cc v v ol (note 19) sda output buffer low voltage, sinking 4ma 00.4v cpin (note 19) a1, a0, a2, sda, and scl pin capacitance 10 pf f scl scl frequency 400 khz t sp pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa (note 19) scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window 900 ns t buf (note 19) time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition 1300 ns t low clock low time measured at the 30% of v cc crossing 1300 ns t high clock high time measured at the 70% of v cc crossing 600 ns t su:sta start condition setup time scl rising edge to sda falling edge; both crossing 70% of v cc 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc 100 ns t hd:dat input data hold time from scl rising edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window 0ns t su:sto stop condition setup time from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc 600 ns t hd:sto stop condition hold time for read, or volatile only write from sda rising edge to scl falling edge; both crossing 70% of v cc 1300 ns t dh (note 19) output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window 0ns t r (note 19) sda and scl rise time from 30% to 70% of v cc 20 + 0.1*cb 250 ns t f (note 19) sda and scl fall time from 70% to 30% of v cc 20 + 0.1*cb 250 ns operating specifications over the recommended operating c onditions unless otherwise spec ified. (continued) symbol parameter test conditions min (note 21) typ (note 5) max (note 21) unit isl22343
8 fn6423.2 august 17, 2015 cb (note 19) capacitive loading of sda or scl total on-chip and off-chip 10 400 pf rpu (note 19) sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2~2.5k ? for cb = 40pf, max is about 15~20k ? 1k ? t su:a a1 and a0 setup time before start condition 600 ns t hd:a a1 and a0 hold time after stop condition 600 ns notes: 5. typical values are for t a = +25c and 3.3v supply voltage. 6. lsb: [v(r w ) 255 C v(r w ) 0 ] / 255. v(r w ) 255 and v(r w ) 0 are v(r w ) for the dcp register set to ff hex and 00 hex respectively. l sb is the incremental voltage when changing from one tap to an adjacent t ap. 7. zs error = v(rw) 0 / lsb. 8. fs error = [v(rw) 255 C v cc ] / lsb. 9. dnl = [v(rw) i C v(rw) i-1 ] / lsb-1, for i = 1 to 255. i is the dcp register setting. 10. inl = [v(rw) i C i ? lsb C v(rw) 0 ]/lsb for i = 1 to 255. 11. v match = [v(rwx)i -v(rwy)i]/lsb, for i = 0 to 255, x = 0 to 3, y = 0 t o 3. 12. for i = 16 to 240 decimal, t = -40c to +125c. max( ) is th e maximum value of the wiper voltage and min ( ) is the minimum value of the wiper voltage o ver the temperature range. 13. mi = | rw 255 C rw 0 | / 255. mi is a minimum increment. rw 255 and rw 0 are the measured resistances for the dcp register set to ff he x and 00 hex respectively. 14. roffset = rw 0 / mi, when measuring between rw and rl. roffset = rw 255 / mi, when measuring between rw and rh. 15. rdnl = (rw i C rw i-1 ) / mi -1, for i = 16 to 255. 16. rinl = [rw i C (mi ? i) C rw 0 ] / mi, for i = 16 to 255. 17. r match = [(rx)i -(ry)i]/mi, for i = 0 to 255, x = 0 to 3, y = 0 to 3. 18. for i = 16 to 240, t = -40c to +125c. max( ) is the maximu m value of the resistance and min ( ) is the minimum value of the resistance over the temperature range. 19. this parameter is not 100% tested. 20. t wc is the time from a valid stop condition at the end of a write sequence of i 2 c serial interface, to the end of the self-timed internal non- volatile wri te cycle. 21. parts are 100% tested at +25c. temperature limits establish ed by characterization and are not production tested. operating specifications over the recommended operating c onditions unless otherwise spec ified. (continued) symbol parameter test conditions min (note 21) typ (note 5) max (note 21) unit tc v max v rw ?? i ?? min v rw ?? i ?? C max v rw ?? i ?? min v rw ?? i ?? + ?? 2 ? --------------------------------------------------------------- ------------------------------ - 10 6 165c ---------------- - ? = + tc r max ri ?? min ri ?? C ?? max ri ?? min ri ?? + ?? 2 ? --------------------------------------------------------------- - 10 6 165c ---------------- - ? = + isl22343
9 fn6423.2 august 17, 2015 dcp macro model sda vs scl timing a2, a1 and a0 pin timing 10pf rh r total c h 25pf c w c l 10pf rw rl t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t sp t hd:a scl sda a2, a1, a0 t su:a clk 1 start stop
10 fn6423.2 august 17, 2015 typical performance curves figure 1. wiper resistance vs tap position [ i(rw) = v cc /r total ] for 10k ? (w) figure 2. standby i cc and i v- vs temperature figure 3. dnl vs tap position in voltage divider mode for 10k ? (w) figure 4. inl vs tap position in voltage divider mode for 10k ? (w) figure 5. zs error vs temperature figure 6. fs error vs temperature 0 10 20 30 40 50 60 70 80 0 50 100 150 200 250 tap position (decimal) wiper resistance ( ? ) t = +25c t = -40c t = +125c -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -40 0 40 80 120 temperature (c) standby current (a) i cc i v- -0.50 -0.25 0 0.25 0.50 0 50 100 150 200 250 tap position (decimal) dnl (lsb) t = +25c v cc = 2.25v v cc = 5.5v -0.50 -0.25 0 0.25 0.50 0 50 100 150 200 250 tap position (decimal) inl (lsb) t = +25c v cc = 5.5v v cc = 2.25v 0 0.4 0.8 1.2 1.6 2.0 -40 0 40 80 120 temperature (oc) zs error (lsb) v cc = 2.25v v cc = 5.5v 50k 10k -5 -4 -3 -2 -1 0 -40 0 40 80 120 temperature (oc) fs error (lsb) v cc = 5.5v 10k 50k v cc = 2.25v isl22343
11 fn6423.2 august 17, 2015 figure 7. dnl vs tap position in rheostat mode for 10k ? (w) figure 8. inl vs tap position in rheostat mode for 10k ? (w) figure 9. end to end r total % change vs temperature figure 10. tc for voltage divider mode in ppm figure 11. tc for rheostat mode in ppm figure 12. frequency response (1mhz) typical performance curves (continued) -0.50 -0.25 0 0.25 0.5 0 50 100 150 200 250 tap position (decimal) rdnl (mi) v cc = 2.25v v cc = 5.5v t = +25c -0.5 0 0.5 1.0 1.5 2.0 0 50 100 150 200 250 tap position (decimal) rinl (mi) v cc = 5.5v t = +25c v cc = 2.25v -0.40 0.00 0.40 0.80 1.20 1.60 -40 0 40 80 120 r total change (%) 10k 5.5v temperature (oc) 2.25v 50k 0 40 80 120 160 200 16 66 116 166 tap position (decimal) tcv (ppm/oc) 216 266 10k 50k 0 100 200 300 400 500 16 66 116 166 216 tap position (decimal) tcr (ppm/oc) 10k 50k wiper at mid point (position 80h) r total = 10k ? output input isl22343
12 fn6423.2 august 17, 2015 pin description potentiometers pins rhi and rli the high (rhi) and low (rli) terminals of the isl22343 are equivalent to the fixed t erminals of a mechanical potentiometer. rhi and rli are r eferenced to the relative position of the wiper and not the voltage potential on the terminals. with wri set to 2 55 decimal, the wiper will be closest to rhi, and with the wri set to 0, the wiper is closest to rli. rwi rwi is the wiper terminal and is equivalent to the movable terminal of a mechanical potenti ometer. the position of the wiper within the array is det ermined by the wri register. bus interface pins serial data input/output (sda) the sda is a bidirectional seri al data input/output pin for i 2 c interface. it receives device address, operation code, wiper address and data from an i 2 c external master device at the rising edge of the serial clock scl, and it shifts out data aft er each falling edge of the serial clock. sda requires an external pull-up resistor, since it is an open drain input/output. serial clock (scl) this input is the serial clock of the i 2 c serial interface. scl requires an external pull-up resistor, since it is an open drai n input. device address (a2, a1, a0) the address inputs are used to set three least significant bits of the 7-bit i 2 c interface slave address. a match in the slave address serial data stream m ust match with the address input pins in order to initi ate communication with the isl22343. a maximum of eight isl22343 devices may occupy the i 2 c serial bus (see table 3). principles of operation the isl22343 is an in tegrated circuit incorporating four dcps with its associated registers, non-volatile memory and an i 2 c serial interface providing direct communication between a host and the potentiometer and memory. the resistor arrays are compris ed of individual resistors connected in a series. at ei ther end of the array and between each resistor is an elec tronic switch that transfers the potential at tha t point to the wiper. the electronic switches on the device operat e in a make before break mode when the w iper changes tap positions. when the device is powered dow n, the last value stored in ivri will be maintained in the non-volatile memory. when power is restored, the contents of the ivri are recalled and loaded into the corresponding wri to set the wipers to their initial positions. dcp description the dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of each dcp are equivalent to the fix ed terminals of a mechanical potentiometer (rhi and rli pins). the rwi pin of the dcp is connected to i ntermediate nodes, and is equivalent to the wiper terminal of a mechanica l potentiometer. the position of the wiper termi nal within the dcp is co ntrolled by an 8-bit volatile wiper register (wr i). when the wri of a dcp contains all zeroes ( wri[7:0]= 00h), its wiper terminal (rwi) is closest to its low terminal (rli). when the wri register of a dcp contains all ones ( wri[7:0] = ffh), its wiper terminal (rwi) is closest to i ts high terminal (rhi). as the value of the wri incr eases from all zer oes (0) to all ones (255 decimal), the wiper m oves monotonically from the position closest to rli to the po sition closest to rhi. at the figure 13. midscale glitch, code 7fh to 80h figure 14. large signal settling time typical performance curves (continued) wiper scl cs wiper unloaded, movement from 0h to ffh isl22343
13 fn6423.2 august 17, 2015 same time, the resistance be tween rwi and rli increases monotonically, while the res istance between rhi and rwi decreases monotonically. while the isl22343 is being powered up, the wri is reset to 80h (128 decimal), which locat es rwi roughly at the center between rli and rhi. after the power supply voltage becomes large enough for reliable non-volatile memory reading, the wri will be reloa ded with the value stored in corresponding non-volatile init ial value register (ivri). the wri and ivri can be read or written to directly using the i 2 c serial interface as describ ed in the following sections. memory description the isl22343 contains four non- volatile 8-bit initial value register (ivri), eleven general purpose non-volatile 8-bit registers and five volatile 8-b it registers: four wiper registe rs (wri) and access control regi ster (acr). memory map of isl22343 is in table 1. the non -volatile registers (ivri) at address 0, 1, 2 and 3 contain in itial wiper pos ition and volati le registers (wri) contain current wiper position. the non-volatile ivri and vol atile wri registers are accessible with th e same address. the access control register ( acr) contains information and control bits described below in table 2. the vol bit (acr[7] ) determines whethe r the access to wiper registers wri or initi al value registers ivri. if vol bit is 0, the non-volatile ivri registers are accessible . if vol bit is 1, only the vo latile wri are accessible. note: value is written to ivri re gister also is written to the corresponding wri. the defaul t value of this bit is 0. the shdn bit (acr[6]) disables o r enables shutdown mode. when this bit is 0, dcps are in shutdown mode. default value of the shdn bit is 1. the wip bit (acr[5]) is a read-onl y bit. it indicates that non- volatile write operation is in progress. it is impossible to wr ite to the wri or acr wh ile wip bit is 1. i 2 c serial interface the isl22343 supports an i 2 c bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and t he receiving device as the receiver. the device controlli ng the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transm it and receive operations. therefore, the isl22343 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of eac h byte of data first. protocol conventions data states on the sda lin e must change only during scl low periods. sda state cha nges during scl high are reserved for indicating st art and stop conditions (see figure 16). on power-up of the isl22343, the sda pin is in the input mode. all i 2 c interface operations m ust begin with a start condition, which is a high to l ow transition of sda while scl is high. the isl22343 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 16). a start condition is ignored during the power- up of the device. all i 2 c interface operations must be terminated by a stop condition, which is a low to h igh transition of sda while table 1. memory map address (hex) non-volatile volatile 10 n/a acr f reserved e general purpose n/a d general purpose n/a c general purpose n/a b general purpose n/a a general purpose n/a 9 general purpose n/a 8 general purpose n/a 7 general purpose n/a 6 general purpose n/a 5 general purpose n/a 4 general purpose n/a 3ivr3 wr3 2ivr2 wr2 1ivr1 wr1 0ivr0 wr0 table 2. access control register (acr) bit # 7 6 5 43210 name vol shdn wip 00000 rli rwi rhi figure 15. dcp connection in shutdown mode isl22343
14 fn6423.2 august 17, 2015 scl is high (see figure 16). a stop condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. an ack (acknowledge) is a software convention used to indicate a succe ssful data transfer. the transmitting device, either master or slave, re leases the sda bus after transmitting eight b its. during the nint h clock cycl e, the receiver pulls the sda l ine low to acknowledge the reception of the eight bits of data (see figure 17). the isl22343 responds with an ack after recognition of a start condition followed by a va lid identification byte, and once again after successful receipt of an address byte. the isl22343 also responds with an ack after receiving a data byte of a write ope ration. the master must respond with an ack after receiving a data byte of a read operation a valid identification byte con tains 1010 as four msbs, and the following three bits matchin g the logic valu es present at pins a2, a1 and a0. the lsb is the read/write bit. its value is 1 for a read operation and 0 for a write operation (see table 3). table 3. identification byte format 1010a2a1a0r/w (msb) (lsb) logic values at pins a2, a1 and a0, respectively sda scl start data data stop stable change data stable figure 16. valid data changes, start and stop conditions sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance figure 17. acknowledge response from receiver high impedance s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the slave a c k 10 1 00 a c k write signal at sda 0000 a0 a1 0 figure 18. byte write sequence a2 isl22343
15 fn6423.2 august 17, 2015 write operation a write operation requires a start condition, followed by a valid identification byte, a valid addre ss byte, a data byte, and a stop condition. after each of the three bytes, the isl22343 responds with an ack . at this time, the device enters its standby st ate (see figure 18). the non-volatile write cycle st arts after stop condition is determined and it requires up t o 20ms delay for the next non-volatile write. thus, non- volatile registers must be written individually. read operation a read operation consist of a t hree byte instruction followed by one or more data bytes ( see figure 19). the master initiates the operation issu ing the following sequence: a start, the identificat ion byte with the r/w bit set to 0, an address byte, a second start, and a second identification byte with the r/w bit set to 1. after each of the three bytes, the isl22343 responds with a n ack. then the isl22343 transmits data bytes as long as the master responds with an ack during the scl cycle foll owing the eight h bit of each byte. the data bytes are from the registers indicated by an internal pointer. this pointers initial value is determined by the address byte in the read operation instruction, and increments by one during transmission of each data byte. after reaching the memory locat ion 0fh, the p ointer rolls over to 00h, and the device co ntinues to output data for each ack received.the mas ter terminates the read operation issuing a nack (ack ) and a stop condition following the last bit of the la st data byte (see figure 19). applications information when stepping up through each tap in voltage divider mode, some tap transition points c an result in noticeable voltage transients (or overshoot/under shoot) resulting from the sudden transition from a very low impedance make to a much higher impedance break within an extremely short period of time (<50ns). two such code transitions are efh to f0h, and 0fh to 10h. note tha t all switching transients will settle well within the settling time as stated on the datasheet . a small capacitor can be ad ded externally to reduce the amplitude of these voltage tr ansients, but that will also reduce the useful bandwidth of t he circuit, thus this may not be a good solution for some a pplications. it may be a good idea, in that case, to use fas t amplifiers in a signal chain fo r fast recovery. application example figure 20 shows an example of using isl22343 for gain setting and offset correction in a high side current measurement application. dcp0 applies a programmable offset voltage of 25mv to the fb+ pin of the instrumentation amplifier isl28272 to adjust outp ut offset to zero voltages. dcp1 programs the gain of t he isl28272 from 90 to 110 with 5v output for 10a curr ent through current sense resistor. dcp2 and dcp3 are used for another channel of dual isl28272 correspondently (not shown in figure 20). more application exampl es can be found at http://www.intersil. com/data/an/an1145.pdf signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 10 1 00 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 0 000 a0 a1 a0 a1 figure 19. read sequence a c k a2 a2 101 0 isl22343
16 fn6423.2 august 17, 2015 rl0 rw0 rh0 in+ in- fb+ fb- v out r 4 150k, 1% r 6 1.37k, 1% v out = 0v to +5v to adc 1/2 isl28272 0.005 ? dc/dc converter output processor load 10a, max 5 6 8 4 2 3 v- v+ +5v 16 programmable gain 90 to 110 en 7 10k 10k 0.1f 1.2v r 5 309, 1% 50k dcp1 (1/4 isl22343u) +5v -5v r 1 50k, 1% r 3 50k, 1% r 2 1k, 1% dcp0 (1/4 isl22343u) rl1 rh1 rw1 50k figure 20. current sensing with gain and offset control programmable offset 25mv isl22343ufv20z rh0 rl0 rw0 rh1 rl1 rw1 vcc scl a2 gnd sda a1 a0 v- +5v -5v 16 5 6 4 15 14 7 17 11 12 13 20 19 18 dcp0 dcp1 i 2 c bus rh2 rl2 rw2 rh3 rl3 rw3 3 2 1 8 9 10 dcp2 dcp3 isl22343
17 all intersil u.s. products are m anufactured, assembled and test ed utilizing iso9001 quality systems. intersil corporations quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products , see www.intersil.com fn6423.2 august 17, 2015 about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change august 17, 2015 fn6423.2 updated ordering information table on page 1. added revision history and about intersil sections. updated pod m20.173 to current revision. changes: converted to new pod format and added land pattern. no dimension changes. isl22343
18 fn6423.2 august 17, 2015 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l20.5x5 20 lead quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - 0.02 0.05 - a2 - 0.65 1.00 9 a3 0.20 ref 9 b 0.23 0.30 0.38 5, 8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7, 8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7, 8 e 0.65 bsc - k0.20 - - - l 0.35 0.60 0.75 8 n202 nd 5 3 ne 5 3 p- -0.609 ? --129 rev. 4 11/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in mill imeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measure d between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provid ed to assist with pcb land patte rn design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & ? are present when anvil singulation method is used and not present for saw singulation. 10. compliant to jedec mo-220vhhc issue i except for the "b" dimension. isl22343
19 fn6423.2 august 17, 2015 isl22343 package outline drawing m20.173 20 lead thin shrink small outline package (tssop) rev 2, 5/10 detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burr s. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include inter lead flash or protrusion. inter lead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrus ion shall be 0.08mm total in excess of dimension at maximum materia l condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. 0.09-0.20 see detail "x" (0.65 typ) (5.65) (0.35 typ) 0.90 +0.15/-0.10 0.60 0.15 0.15 max 0.05 min plane gauge 0-8 0.25 1.00 ref (1.45) 20 0.20 c b a 2 1 3 9 b 1 3 10 a pin #1 i.d. mark 6.50 0.10 6.40 4.40 0.10 0.65 0.10 c seating plane 0.25 +0.05/-0.06 5 c h - 0.05 1.20 max 0.10 c b a m

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